Field effect transistors are comprised of a pair of diffusion regions, referred to as a source and a drain, spaced apart within a semiconductive substrate. Such include a gate provided adjacent the separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate area adjacent the gate and between the diffusion regions is referred to as the channel. The semiconductive substrate typically comprises a bulk monocrystalline silicon substrate having a light conductivity dopant impurity concentration. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material (typically monocrystalline silicon) over an underlying insulating layer. Such are commonly referred to as semiconductor-on-insulator (SOI) constructions.
The diffusion regions in SOI can extend completely or partially through the thin silicon layer. Further, the SOI device can operate in a partially depleted or fully depleted mode. Such refers to the depletion region formed in the SOI layer when the channel region is inverted by applied voltage. If the depletion region extends through the entire SOI layer, the device is considered to be fully depleted. If on the other hand the depletion region extends only partly through the SOI layer, the device is considered to be partially depleted. Usually, the source and drain regions in a partially depleted device extend only partially through the SOI layer. Usually, the source and drain regions in a fully depleted device extend completely through the SOI layer.
Integrated circuitry fabrication technology continues to strive to increase circuit density, and thereby minimize the size and channel lengths of field effect transistors. Improvements in technology have resulted in reduction of field effect transistor size from long-channel devices (i.e., channel lengths greater than 2 microns) to short-channel devices (i.e., channel lengths less than 2 microns).
In an n-type (NMOS) device, when the gate voltage is above the threshold voltage, and the drain voltage becomes sufficiently high so that the device is in the saturation region, the inversion region in the channel becomes pinched off near the drain and electrons are accelerated across this pinch-off region from the channel to the drain. At certain gate and drain bias conditions, the electric fields in the pinch-off region are high enough to cause the accelerated electrons to impact into substrate atoms. The result of this impact is the generation of additional electron-hole pairs. The electrons flow either into the gate oxide or gate conductor, or to the drain. The holes flow into the substrate. In bulk MOS devices, these excess holes are collected at a substrate tie. A substrate tie constitutes a fourth terminal of a MOS device and controls the substrate bias of the device. If the substrate tie terminal is at a large distance from the device, or if the generated holes are of a very high number, excess holes collect under the device's channel region.
These excess holes locally bias the substrate to a potential that is higher than that being provided at the substrate tie. If this higher potential rises above the source potential of the NMOS device, the source/body junction becomes forward biased and a parasitic n-p-n bipolar device is turned "on". The source acts as the emitter, the body is the base, and the drain is the collector. At this point, the NMOS device has entered what is referred to as the "snap-back" regime, and the drain current rises significantly above the intrinsic saturation current of the device. Operating an NMOS device in snap-back significantly reduces its lifetime, and is not a preferred mode of operation in typical integrated circuits.
Snap-back is a much larger concern with partially depleted SOI devices because there is no substrate tie to collect excess holes that are generated, during impact ionization. Therefore, the substrate rises much sooner and the snap-back voltage is reduced when compared to an equivalent bulk-MOS device. Further, in SOI a common electrical characteristic observed is the "kink" effect. This is a result of the same phenomenon as snap-back, but occurs at lower drain electric fields. The "kink" in the SOI MOS devices Id-Vd curves (when the device is in saturation) is the result of a rise in the substrate potential due to hole injection from impact ionization at the drain. The holes do not cause forward bias of the source/substrate junction, but the small rise in substrate potential causes the threshold voltage of the MOS device to slightly decrease, thereby increasing the drain current and causing the kink Id-Vd characteristics.
Again, one prior art way of countering this phenomena is to add a conductive substrate tie to collect excess holes that are injected into the substrate. This prevents local biasing of the substrate, and therefore prevents the kink effect and increases the snapback voltage. In bulk devices, this substrate contact can be made anywhere in the vicinity of the device since the substrate is continuous from the substrate tie to the device body. However in SOI devices, the device body may be isolated from adjacent devices. To make body contact to such a device, an added p+ active area is abutted to the typical n+ source of an n-channel device. The p+ active area adjacent to or within the n+ source makes ohmic contact to the body of the device. However, it requires additional area, and a method to contact the p+ region as well as the n+ regions.
Another method for making this body contact in SOI is to not completely isolate one field effect transistor region from another. This, however, eliminates one of the major advantages of SOI, that of being able to reduce active area spacing from n-channel to p-channel devices.
It would be desirable to develop a method to provide the substrate electrical contact to completely isolated devices without requiring added layout area.